1. Field of the Invention
The present invention relates generally to apparatus that apply pressure to the backsides of semiconductor device structures during polishing or planarization of one or more layers thereof. Particularly, the present invention relates to apparatus that selectively apply different amounts of pressure to different locations on the backsides of semiconductor device structures as one or more layers on the opposite, active surfaces thereof are polished or planarized. More particularly, the present invention relates to apparatus that employ magnetic fields to independently apply pressure to different, selected locations on the backside of a semiconductor device structure. The present invention also relates to polishing methods wherein different amounts of pressure are selectively applied to different locations on the backside of a semiconductor device structure, as well as to systems for effecting such methods.
2. Background of Related Art
Chemical-mechanical polishing and chemical-mechanical planarization are abrasive techniques that typically include the use of a combination of chemical and mechanical agents to planarize, or otherwise remove material from, a surface of a semiconductor material substrate bearing devices under fabrication. Such a structure may be referred to for the sake of convenience as a “semiconductor device structure.” A chemical component, typically a slurry that includes one or more oxidizers, abrasives, complexing agents, and inhibitors, oxidizes the surface of one or more material layers that are being polished or planarized (i.e., at least partially removed). A polishing pad, or CMP pad, is used with the slurry and, along with abrasives present in the slurry, effects mechanical removal of the layer or layers from the surface of the semiconductor device structure. It should be noted that abrasive-only polishing and planarization, e.g., without the use of active chemical agents to effect material removal, are becoming more prevalent due to environmental concerns. Thus, the term “CMP” as used herein encompasses such abrasive-only methods and apparatus.
Conventional CMP pads are round and planar and have larger dimensions than the semiconductor substrates (e.g., wafers or other substrates including silicon, gallium arsenide, indium phosphide, etc.) upon which the structures or layers to be polished have been formed. In polishing one or more layers of structures formed on a substrate, the substrate and the conventional CMP pad are rotated relative to one another, with the location of the substrate being moved continuously relative to the polishing surface of the pad so that different areas of the pad are used to polish one or more of the layers or structures formed on the substrate.
When conventional polishing processes are used, the surface of a semiconductor device structure following polishing thereof is often not planar. Due to the rotation of at least the semiconductor device structure during polishing, the periphery of the semiconductor device structure moves at a faster rate than the center thereof. Thus, material is removed from the periphery of a rotated semiconductor device structure more quickly than material is removed from more central regions of the semiconductor device structure.
In addition, although the inhibitors of a slurry function to even out the polishing rate across nonplanar surfaces, polishing of structures with initially great differences in height may not result in a planar surface, but may result in a surface with raised “rings”.
As exemplified by U.S. Pat. No. 6,050,882 to Chen (hereinafter “Chen”), attempts have been made to increase the planarity to which semiconductor device structures are polished. Chen discloses a wafer carrier head apparatus that includes independently movable rods. Rods that are located outside of the periphery of a semiconductor device structure assembled with the carrier head extend at least partially downward to laterally confine the semiconductor device structure during polishing of one or more layers thereof. Rods that contact the backside of the semiconductor device structure are biased against all locations of the backside with equal amounts of pressure or force provided by positive air pressure applied to a single pressurizable bladder located above all of the rods. Chen also discloses another embodiment of the carrier head, wherein a pressurizable chamber may be located centrally relative to the rods so as to apply pressure to the central region of a semiconductor device structure assembled with the carrier head or to act as a vacuum chuck when a negative pressure is applied to the chamber. The chamber may be used to apply a different amount of pressure to the backside of the semiconductor device structure than that applied to the peripheral regions of the backside of the semiconductor device structure by the rods. Nonetheless, the carrier heads of Chen do not facilitate the application of different amounts of pressure to different, selected locations on the backside of a semiconductor device structure in response to preventing nonplanarities at specific locations on the active surface of the semiconductor device structure. More over, as the carrier heads of Chen are configured to apply only one or two different amounts of pressure to a semiconductor device structure during polishing thereof, these carrier heads will not adequately compensate for nonplanarities that may be formed during polishing bu t, rather, may accentuate these nonplanarities.
Accordingly, it appears that the art lacks apparatus for applying selected amounts of pressure to one or more different, selected locations on the backsides of semiconductor device structures during polishing thereof, as well as methods for selectively applying pressure to selected locations on the backside of a semiconductor device structure during polishing thereof